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华邦 W631GG6MB

W631GG6MB

Density64Mbitx16 8BanksStatus
Vcc1.5V±0.075VFrequency667 / 800 / 933 / 1066 MHz
PackageTemperature RangeC-temp, I-temp, Automotive
Feature ListThe W631GG6MB is a 1G bits DDR3 SDRAM and speed involving -09, 09I, 09J, -11, 11I, 11J, -12, 12I, 12J, -15, 15I and 15J


产品特点
Power Supply: VDD, VDDQ = 1.5 V ± 0.075 V 
Double Data Rate architecture: two data transfers per clock cycle 
Eight internal banks for concurrent operation 
8 bit prefetch architecture 
CAS Latency: 5, 6, 7, 8, 9,10,11,13 and 14 
Burst Length 8(BL8) and burst chop 4 (BC4) modes: fixed via mode register (MRS) or selectable On-The-Fly (OTF) 
Programmable read burst ordering: interleaved or nibble sequential 
Bi-directional, differential data strobes (DQS and /DQS# ) are transmitted / received with data 
Edge-aligned with Read data and center-aligned with Write data 
DLL aligns DQ and DQS transitions with clock 
Differential clock inputs (CK and /CK# ) 
Commands entered on each positive CK edge, data and data mask are referenced to both edges of a differential data strobe pair (double data rate)
Posted CAS with programmable additive latency (AL = 0, CL - 1 and CL - 2) for improved command, address and data bus efficiency 
Read Latency = Additive Latency plus CAS Latency (RL = AL + CL) 
Auto-precharge operation for read and write bursts 
Refresh, Self-Refresh, Auto Self-refresh (ASR) and Partial array self refresh (PASR) 
Precharged Power Down and Active Power Down 
Data masks (DM) for write data 
Programmable CAS Write Latency (CWL) per operating frequency 
Write Latency WL = AL + CWL 
Multi purpose register (MPR) for readout a predefined system timing calibration bit sequence 
System level timing calibration support via write leveling and MPR read pattern 
ZQ Calibration for output driver and ODT using external reference resistor to ground 
Asynchronous RESET# pin for Power-up initialization sequence and reset function 
Programmable on-die termination (ODT) for data, data mask and differential strobe pairs 
Dynamic ODT mode for improved signal integrity and preselectable termination impedances during writes
2K Byte page size 
Interface: SSTL_15
Package VFBGA96 Ball (7.5x13mm2), RoHS compliant

编辑:admin  最后修改时间:2018-05-30   浏览:4

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